The present invention relates generally to semiconductor microstructures and fabrication methods, and more particularly, to methods of forming oxide masks on substrates that have submicron openings therein and which are formed using conventional optolithography techniques, and microstructures formed using the methods, including microstructures having high aspect ratio submicron trenches formed therein.
Deep-sub-micron vertical gaps are required in certain MEMS devices to increase the capacitive electromechanical coupling. Higher coupling results in higher signal to noise ratio in sensors and lower equivalent motional impedance in electromechanical resonators.
High Q integrated micromechanical resonators are of great interest as viable substitutes for bulky and off-chip mechanical vibrating components in a variety of data processing, sensory and frequency synthesis applications. A great challenge in extending the frequency of capacitive micromechanical resonators into the RF range is maintaining acceptable impedance level and power handling capability. As the resonators are reduced in size to achieve higher frequencies, less area is available for capacitive signal transduction. In order to overcome this limitation and increase the transducer capacitance, ultra-thin inter-electrode gap spacing is required. This is discussed by S. Y. No and F. Ayazi in “The HARPSS Process for Fabrication of Nano-Precision Silicon Electromechanical Resonators”. IEEE Conf. on Nanotechnology, 10/28–30/01, (2001), pp. 489–494. Therefore, low-cost manufacturing techniques that can implement high-Q capacitive resonators with scalable gap spacing in the 100 nm range are of great interest.
Papers have previously been published discussing capacitive single crystal silicon resonators with polysilicon electrodes and ultra-thin transducer gaps. See, for example, S. Pourkamali and F. Ayazi, “SOI-based HF and VHF single crystal silicon resonators with sub-100 nm vertical capacitive gaps”. Transducers '03, pp. 837–840, S. Pourkamali, et al, “High-Q Single Crystal Silicon HARPSS Capacitive Beam Resonators with Self-Aligned Sub-100 nm Transduction Gaps”, Journal of Micro Electro Mechanical Systems. August 2003, pp. 487–496, and S. Y. No, et al. “Single crystal silicon HARPSS capacitive resonators with submicron gap spacings”, proceedings, Hilton Head 2002, pp. 281–284. The resonators were fabricated using the HARPSS process, and the transducer gaps were created by removing a thin silicon-dioxide sacrificial layer in hydrofluoric acid (HF). Surface micromachined resonators are discussed by K. Wang, et al, “VHF free-free beam high-Q micromechanical resonators”, JMEMS, Vol. 9, No. 3, September 2000.
All of these previously reported processes capable of defining deep-sub-micron gaps are multi-mask fabrication sequences involving multiple deposition/etching steps. In these processes gaps are usually defined by the thickness of a sacrificial layer. As DRIE techniques improve and higher aspect ratio trenches with smaller width become achievable, dry-etching of trenches for implementation of sub-micron capacitive gaps becomes increasingly attractive. This will potentially simplify the fabrication process and enable implementation of all single crystal silicon devices. However, there are some challenges. Mask formation for dry-etching of sub-micron feature sizes is not trivial and demands for expensive state of the art optical lithography equipments. The other limiting factor is the selectivity of the etching process to the mask material. The trench depth, assuming availability of very high aspect ratio etching processes (AR>50:1), can be restricted by the mask thickness and not necessarily by the aspect ratio of the etch process.
Several US patents address submicron trenches or gaps. These include U.S. Pat. No. 4,449,287, issued May 22, 1984, entitled “Method of Providing a Narrow Groove or Slot in a Substrate Region, in Particular a Semiconductor Substrate region”, U.S. Pat. No. 4,735,681, issued Apr. 5, 1988, entitled “Fabrication Method for Sub-Micron Trench”, and U.S. Pat. No. 5,851,887, issued Dec. 22, 1998, entitled “Deep Sub-Micron Polysilicon Gap Formation.”